Zijie Tian 3100724666 📝 docs: add nsys wrong event order bug investigation ...

- Document ring buffer pipeline triggering nsys timestamp bug
- Update profile_offload.sh to use test_ruler.py with options
- Add reference to new doc in CLAUDE.md

Root cause: 4-slot ring buffer pipeline (4 transfer streams +
1 compute stream) triggers event ordering bug in nsys < 2024.2

Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>

2026-01-24 04:32:05 +08:00

..

export_traces.sh

[WIP] NEED to modify communication.

2025-12-24 21:57:51 +08:00

profile_offload.sh

📝 docs: add nsys wrong event order bug investigation

2026-01-24 04:32:05 +08:00